With the continuous development of semiconductor process technology, technology nodes have become smaller and smaller; and requirements on materials have become higher and higher. In an existing field-effect transistor (FET), doping type and doping concentration of the source region and the drain region are different from doping type and concentration of the channel region, thus PN junctions are formed between the source/drain regions and the channel region. With the continuous shrinkage of the critical dimension of semiconductor devices having PN junctions, problems including threshold voltage drifting and leakage current increasing, etc., have become more and more obvious. Thus, novel device structures, such as silicon on insulator, double-gate, triple-gate, or circular gate, etc., have been developed. These novel structures are used to prevent undesired effects, such as short-channel effects, etc.
Areas of the source region, the drain region and the channel region of the FET are reduced because of the continuous shrinkage of the FET. Thus, it may increase difficulties to control the doping process to form the source region, the drain region and the channel region, etc.; and forming PN junctions between the source region and the channel region and between the drain region and the channel region becomes more and more difficult. Therefore, junction-less transistors, which have a same doping type for source regions, drain regions and channel regions, have been developed to overcome abrupt-doping-change problems of the PN junctions. Further, the junction-less transistors are also be able to prevent the short-channel effect, thus the junction-less transistors with a size of a few nanometers may still function well.
However, resistances of the channel regions of the junction-less transistors may be relatively large; and may affect their performance. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.